Desenvolvimento de Macrocélulas Lógicas Modulares em FPGA para Controle Automatizado de Processos

Abstract

This study describes the Development of Modular Logic Macrocells in FPGA for Automated Process Control. It presents the creation of reusable macrocells, which are hardware blocks synthesized and configured within the FPGA itself, and which can be instantiated multiple times for use in different parts of the process, developed through graphical diagrams (BDF) and VHDL language. The proposal is applied to a didactic plant that simulates a material mixing and transfer process, allowing the exploration of sequential digital control practices. The adopted modular approach aims to facilitate logical implementation, reduce development complexity, and promote greater accessibility to FPGA technology for professionals with different levels of familiarity with hardware description languages. The implemented logic was structured into control stages involving timing, sensor reading, and actuator activation. Practical validation demonstrated the expected functionality of the proposed solution, with stable operation consistent with the defined objectives. The obtained results confirm the feasibility of applying macrocells in didactic automation systems, reinforcing the potential of FPGA use in educational and industrial projects.